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Datasheet,Version 2.3, April 27, 2010
C o o l S E T - Q1
ICE2QR0665
(R)
Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V Startup Cell/Depletion C o o l M O S (R) In DIP-8
Power Management & Supply
Never
stop
thinking.
CoolSET(R) - Q1 ICE2QR0665 Revision History: Previous Version: Page 12 12 12
April 27, 2010 2.2 Subjects (major changes since last revision) maximum value for VZC changed to 5.5V maximum value for VFB changed to 5.5V maximum value for VCS changed to 5.5V
Datasheet
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com CoolMOS(R), CoolSET(R) are trademarks of Infineon Technologies AG.
Edition 2010-04-27 Published by Infineon Technologies AG 81726 Munchen, Germany
(c) Infineon Technologies AG 4/27/10. All Rights Reserved.
Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CoolSET(R) - Q1 ICE2QR0665
Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V Startup Cell/Depletion CoolMOS(R) In DIP8
Product Highlights
* * * * * * * * * * * * * * * Quasi resonant operation Active Burst Mode to reach the lowest standby power requirement <100mW@no load Digital frequency reduction for better overall system efficiency Integrated 650V startup cell
PG-DIP-8-6
Features
650V avalanche rugged CoolMOS(R) with built-in startup cell Quasiresonant operation till very low load Active burst mode operation for low standby input power (< 0.1W) Digital frequency reduction with decreasing load for reduced switching loss Built-in digital soft-start Foldback point correction and cycle-by-cycle peak current limitation Maximum on/off time limitation Auto restart mode for VCC Overvoltage and Undervoltage protections Auto restart mode for overload protection Auto restart mode for overtemperature protection Latch-off mode for adjustable output overvoltage protection and transformer short-winding protection
Description
The CoolSET(R)-Q1 series (ICE2QRxx65) is the first generation of quasi-resonant integarted power ICs. It is optimized for off-line switch mode power supply applications such as LCD monitor, DVD R/W, DVD Combo, Blue-ray DVD, set top box, etc. Operting the MOSFET switch in quasi-resonant mode, lower EMI, higher efficiency and lower voltage stress on secondary diodes are expected for the SMPS. Based on the BiCMOS technology, the CoolSET(R)-Q1 series has a wide operation range (up to 25V) of IC power supply and lower power consumption. It also offers many advantages such as: a quasi-resonant operation till very low load increasing the average system efficiency compared to other conventional solutions; the Active Burst Mode operation enables an ultra-low power consumption at standby mode with small and controllable output voltage ripple.
Cbus 85 ~ 265 VAC CZC RZC2 RZC1
Snubber
Wp Ws
DO CO
Lf
Cf VO
Dr1~Dr4
RVCC DVCC CVCC
Wa
ZC
VCC
Drain
CPS Rb1
Power Management PWM controller Current Mode Control Cycle-by-Cycle current limitation Zero Crossing Block Active Burst Mode Protections
Startup Cell
CS
Depl. CoolMOS(R) Power Cell
RCS Optocoupler
Rb2
Rovs1
GND
Rc1
FB
TL431 Cc1 Cc2 Rovs2
Control Unit
CoolSET(R)-Q1
VDS 650V RDSon1) 0.65
Type ICE2QR0665
1) 2)
Package PG-DIP-8-6
Marking ICE2QR0665
230VAC 15%2) 88W
85-265 VAC2) 50W
typ @ T=25C Calculated maximum input power rating at Ta=50C, Ti=125C and without copper area as heat sink.
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Table of Contents 1 1.1 1.2 1.3 2 3 3.1 3.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.2 3.4 3.4.1 3.5 3.5.1 3.5.2 3.5.3 3.6 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 5 6 7 Page 5 5 5 5
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC Pre-Charging and Typical VCC Voltage During Start-up . . . . . . . . . . . . . . . . 7 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Up/down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Zero crossing (ZC counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ringing suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switch Off Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Entering Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 During Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Leaving Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CoolMOS(R) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 13 14 14 14 14 15 15 16 16
Typical CoolMOS(R) Performance Characteristic . . . . . . . . . . . . . . . . . . . . . . . . 17 Input power curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
Pin Configuration with PG-DIP-8-6 1.3 Pin Functionality
ZC (Zero Crossing) At this pin, the voltage from the auxiliary winding after a time delay circuit is applied. Internally, this pin is connected to the zero-crossing detector for switch-on determination. Additionally, the output overvoltage detection is realized by comparing the voltage Vzc with an internal preset threshold. FB (Feedback) Normally, an external capacitor is connected to this pin for a smooth voltage VFB. Internally, this pin is connected to the PWM signal generator for switch-off determination (together with the current sensing signal), the digital signal processing for the frequency reduction with decreasing load during normal operation, and the Active Burst Mode controller for entering Active Burst Mode operation determination and burst ratio control during Active Burst Mode operation. Additionally, the open-loop / over-load protection is implemented by monitoring the voltage at this pin. CS (Current Sense) This pin is connected to the shunt resistor for the primary current sensing, externally, and the PWM signal generator for switch-off determination (together with the feedback voltage), internally. Moreover, shortwinding protection is realised by monitoring the voltage Vcs during on-time of the main power switch. Drain (Drain of integrated Depl. CoolMOS(R)) Drain pin is the connection to the drain of the internal Depl. CoolMOS(R). VCC (Power supply) VCC pin is the positive supply of the IC. The operating range is between VVCCoff and VVCCOVP. GND (Ground) This is the common ground of the controller.
Pin 1 2 3 4, 5 6 7 8
1)
Symbol ZC FB CS Drain n.c. VCC GND
Function Zero Crossing Feedback Current Sense/ 650V1) Depl. CoolMOS(R) Source 650V1) Depl. CoolMOS(R) Drain Not connected Controller Supply Voltage Controller Ground
at Tj=110C
1.2
Package PG-DIP-8-6
ZC
1
8
GND
FB
2
7
VCC
CS
3
6
n.c.
Drain
4
5
Drain
Figure 1
Pin Configuration PG-DIP-8-6 (top view)
Note: Pin 4 and 5 are shorted
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2
Figure 2
VCC
Zero Crossing
Undervoltage Lockout
18V
Drain
Startup Cell Internal Bias OTP
Version 2.3
Power M anagem ent
&
10.5
VZCC Voltage Reference
ZC
Depl. CoolM (R) OS G1 Protection
VVCCOVP
C1
clk
ZC counter
D1
Count=7
Com parator C12
10us 1 SQ
Up/down counter G7
tCOUNT
PW Control M
1
R Autorestart Protect SQ
Representative Block diagram
Soft-start
R latched Protect
G2
C2
VZCOVP
Delay tZCOVP
C3 Ringing Suppression
& G 5 1 TOffMax S
VZCRS
Representative Blockdiagram
6
G4 G8
1 R Q & G 6
C4
tOLP_B
VFBOLP
& G9
Gate Drive
C5 G3
en
VFBR1 fsB OSC
TOnMax
GND
Gate Driver C14
VCSSW
C6
VFBZH
VREF
C7 C13 VCSB
VFBZL
Regulation
RFB
Delay tCSSW
FB
Active Burst M ode
25kO
C8 q
tBEB
2pF
VFBEB
C9
VPWM
PW M Com parator PW OP M
GPWM
C15
Foldback Correction
10kO 1pF D2
Leading Edge Blanking tLEB
CS
VFBBOn
C10 Current M ode
Representative Blockdiagram
CoolSET(R) - Q1 ICE2QR0665
April 27, 2010
VFBBOff
Active Burst Block
Current Lim iting
CoolSET(R) - Q1 ICE2QR0665
Functional Description
3
3.1
Functional Description
VCC Pre-Charging and Typical VCC Voltage During Start-up 3.2 Soft-start
As shown in Figure 4, at the time ton, the IC begins to operate with a soft-start. By this soft-start the switching stresses for the switch, diode and transformer are minimised. The soft-start implemented in ICE2QR0665 is a digital time-based function. The preset soft-start time is 12ms with 4 steps. If not limited by other functions, the peak voltage on CS pin will increase step by step from 0.32V to 1V finally.
Vcs_sst (V) 1.00
In ICE2QR0665, a startup cell is integrated into the depletion CoolMOS(R). As shown in Figure 2, the start cell consists of a high voltage device and a controller, whereby the high voltage device is controlled by the controller. The startup cell provides a pre-charging of the VCC capacitor till VCC voltage reaches the VCC turned-on threshold VVCCon and the IC begins to operate. Once the mains input voltage is applied, a rectified voltage shows across the capacitor Cbus. The high voltage device provides a current to charge the VCC capacitor Cvcc. Before the VCC voltage reaches a certain value, the amplitude of the current through the high voltage device is only determined by its channel resistance and can be as high as several mA. After the VCC voltage is high enough, the controller controls the high voltage device so that a constant current around 1mA is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold VVCCon. As shown as the time phase I in Figure 3, the VCC voltage increase near linearly and the charging speed is independent of the mains voltage level.
VVCC VVCCon VVCCoff i ii iii
0.83 0.66 0.49 0.32
ton
3
6
9
12
Time(ms)
Figure 4
Maximum current sense voltage during softstart
3.3
Normal Operation
t1
t2
t
Figure 3
VCC voltage at start up
The time taking for the VCC pre-charging can then be approximately calculated as: t V VCCon C vcc = ----------------------------------------I VCCch arg e2 [1]
The PWM controller during normal operation consists of a digital signal processing circuit including an up/down counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit including a current measurement unit and a comparator. The switch-on and -off time points are each determined by the digital circuit and the analog circuit, respectively. As input information for the switch-on determination, the zero-crossing input signal and the value of the up/down counter are needed, while the feedback signal VFB and the current sensing signal VCS are necessary for the switch-off determination. Details about the full operation of the PWM controller in normal operation are illustrated in the following paragraphs. 3.3.1 Digital Frequency Reduction As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a comparator. These three parts are key to implement digital frequency reduction with decreasing load. In addition, a ringing suppression time controller is implemented to avoid mistriggering by the high frequency oscillation, when the output voltage is very low under conditions such as soft start or output short circuit . Functionality of these parts is described as in the following. 3.3.1.1 Up/down counter The up/down counter stores the number of the zero crossing to be ignored before the main power switch is switched on
1
where IVCCcharge2 is the charging current from the startup cell which is 1.05mA, typically. Exceeds the VCC voltage the turned-on threshold VVCCon of at time t1, the startup cell is switched off, and the IC begins to operate with a soft-start. Due to power consumption of the IC and the fact that still no energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives then energy from the auxiliary winding from the time point t2 on. The VCC then will reach a constant value depending on output load.
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Functional Description
after demagnetisation of the transformer. This value is fixed according to the feedback voltage, VFB, which contains information about the output power. Indeed, in a typical peak current mode control, a high output power results in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according to VFB, the value in the up/down counter is changed to vary the power MOSFET offtime according to the output power. In the following, the variation of the up/down counter value according to the feedback voltage is explained. The feedback voltage VFB is internally compared with three threshold voltages VRL, VRH and VRM, at each clock period of 48ms. The up/down counter counts then upward, keep unchanged or count downward, as shown in Table 1. Table 1 vFB Always lower than VFBZL Once higher than VFBZL, but always lower than VFBZH Once higher than VFBZH, but always lower than VFBR1 Once higher than VFBR1 Operation of the up/down counter up/down counter action Count upwards till 7 Stop counting, no value changing Count downwards till 1 Set up/down counter to 1 VFBZH, are changed internally depending on the line voltage levels.
clock T=48ms
VFB VFBR1 VFBZH VFBZL Up/down counter Case 1 Case 2 Case 3
t
t n+1 n+2 n+2 n+2 n+2 n+1 n-1 n n 4 2 5 1
4 2 7
5 3 7
6 4 7
6 4 7
6 4 7
6 4 7
5 3 6
31 11 41
Figure 5
Up/down counter operation
In the ICE2QR0665, the number of zero crossing is limited to 7. Therefore, the counter varies between 1 and 7, and any attempt beyond this range is ignored. When VFB exceeds VFBR1 voltage, the up/down counter is initialised to 1, in order to allow the system to react rapidly to a sudden load increase. The up/down counter value is also intialised to 1 at the start-up, to ensure an efficient maximum load start up. Figure 5 shows some examples on how up/down counter is changed according to the feedback voltage over time. The use of two different thresholds VFBZL and VFBZH to count upward or downward is to prevent frequency jittereing when the feedback voltage is close to the threshold point. However, for a stable operation, these two thresholds must not be affected by the foldback current limitation (see Section 3.4.1), which limits the VCS voltage. Hence, to prevent such situation, the threshold voltages, VFBZL and
3.3.1.2 Zero crossing (ZC counter) In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network, which provides a time delay to the voltage from the auxiliary winding. Internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller. During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping network, the voltage at the pin is clamped to certain level. The ZC counter has a minimum value of 0 and maximum value of 7. After the internal MOSFET is turned off, every time when the falling voltage ramp of on ZC pin crosses the 100mV threshold, a zero crossing is detected and ZC counter will increase by 1. It is reset every time after the DRIVER output is changed to high. The voltage vZC is also used for the output overvoltage protection. Once the voltage at this pin is higher than the threshold VZCOVP during off-time of the main switch, the IC is latched off after a fixed blanking time. To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network (the RC network consists of Dzc, Rzc1, Rzc2 and Czc as shown in typical application circuit) before it is applied to the zero-crossing detector through the ZC pin. The needed time delay to the main oscillation signal t should be approximately one fourth of the oscillation period (by transformer primary inductor and drainsource capacitor) minus the propagation delay from
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Functional Description
thedetected zero-crossing to the switch-on of the main switch tdelay, theoretically: T osc t = ------------ - t delay 4 [2] To avoid mistriggering caused by the voltage spike across the shunt resistor at the turn on of the main power switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time. In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from going too low because of long on time.
This time delay should be matched by adjusting the time constant of the RC network which is calculated as: =C R R zc1 zc2 -------------------------------zc R + R zc2 zc1 [3]
td
3.4
3.3.1.3 Ringing suppression time After MOSFET is turned off, there will be some oscillation on VDS, which will also appear on the voltage on ZC pin. To avoid that the MOSFET is turned on mistriggerred by such oscillations, a ringing suppression timer is implemented. The time is dependent on the voltage vZC. When the voltage vZC is lower than the threshold VZCRS, a longer preset time applies, while a shorter time is set when the voltage vZC is higher than the threshold. 3.3.1.4 Switch on determination After the gate drive goes to low, it can not be changed to high during ring suppression time. After ring suppression time, the gate drive can be turned on when the ZC counter value is higher or equal to up/down counter value. However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps very fast and IC can not detect enough zero crossings and ZC counter value will not be high enough to turn on the gate drive. In this case, a maximum off time is implemented. After gate drive has been remained off for the period of TOffMax, the gate drive will be turned on again regardless of the counter values and VZC. This function can effectively prevent the switching frequency from going lower than 20kHz, otherwise which will cause audible noise, during start up. 3.3.2 Switch Off Determination In the converter system, the primary current is sensed by an external shunt resistor, which is connected between low-side terminal of the main power switch and the common ground. The sensed voltage across the shunt resistor vCS is applied to an internal current measurement unit, and its output voltage V1 is compared with the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a result, the main power switch is switched off. The relationship between the V1 and the vCS is described by: V 1 = 3.3 V cs + 0.7 [4]
Current Limitation
There is a cycle by cycle current limitation realized by the current limit comparator to provide an overcurrent detection. The source current of the MOSFET is sensed via a sense resistor RCS. By means of RCS the source current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an internal voltage limit, adjusted according to the Mains voltage, the comparator immediately turns off the gate drive. To prevent the Current Limitation process from distortions caused by leading edge spikes, a Leading Edge Blanking time (tLEB) is integrated in the current sensing path. A further comparator is implemented to detect dangerous current levels (VCSSW) which could occur if one or more transformer windings are shorted or if the secondary diode is shorted. To avoid an accidental latch off, a spike blanking time of tCSSW is integrated in the output path of the comparator . 3.4.1 Foldback Point Correction When the main bus voltage increases, the switch on time becomes shorter and therefore the operating frequency is also increased. As a result, for a constant primary current limit, the maximum possible output power is increased, which the converter may have not been designed to support. To avoid such a situation, the internal foldback point correction circuit varies the VCS voltage limit according to the bus voltage. This means the VCS will be decreased when the bus voltage increases. To keep a constant maximum input power of the converter, the required maximum VCS
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Functional Description
versus various input bus voltage can be calculated, which is shown in Figure 6.
1
about Active Burst Mode operation are explained in the following paragraphs. 3.5.1 Entering Active Burst Mode Operation For determination of entering Active Burst Mode operation, three conditions apply: * the feedback voltage is lower than the threshold of VFBEB(1.25V). Accordingly, the peak current sense voltage across the shunt resistor is 0.17; * the up/down counter is 7; and * a certain blanking time (tBEB). Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the controller enters Active Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation prevents mistriggering of entering Active Burst Mode operation, so that the controller enters Active Burst Mode operation only when the output power is really low during the preset blanking time. 3.5.2 During Active Burst Mode Operation After entering the Active Burst Mode the feedback voltage rises as VOUT starts to decrease due to the inactive PWM section. One comparator observes the feedback signal if the voltage level VBH (3.6V) is exceeded. In that case the internal circuit is again activated by the internal bias to start with swtiching. Turn-on of the power MOSFET is triggered by the timer. The PWM generator for Active Burst Mode operation composes of a timer with a fixed frequency of 50kHz, typically, and an analog comparator. Turn-off is resulted by comparison of the voltage signal v1 with an internal threshold, by which the voltage across the shunt resistor VcsB is 0.34V, accordingly. A turn-off can also be triggered by the maximal duty ratio controller which sets the maximal duty ratio to 50%. In operation, the output flip-flop will be reset by one of these signals which come first. If the output load is still low, the feedback signal decreases as the PWM section is operating. When feedback signal reaches the low threshold VBL(3.0V), the internal bias is reset again and the PWM section is disabled until next time regultaion siganl increases beyond the VBH threshold. If working in Active Burst Mode the feedback signal is changing like a saw tooth between 3.0V and 3.6V shown in Figure 8. 3.5.3 Leaving Active Burst Mode Operation The feedback voltage immediately increases if there is a high load jump. This is observed by one comparator. As the current limit is 34% during Active Burst Mode a certain load is needed so that feedback voltage can exceed VLB (4.5V). After leaving active busrt mode, maximum current can now be provided to stabilize VO. In addition, the up/down counter will be set to 1 immediately after leaving Active Burst
0.9 Vcs-max(V)
0.8
0.7
0.6 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 Vin(V)
Figure 6
Variation of the VCS limit voltage according to the IZC current
According to the typical application circuit, when MOSFET is turned on, a negative voltage proportional to bus voltage will be coupled to auxiliary winding. Inside CoolSET(R) - Q1, an internal circuit will clamp the voltage on ZC pin to nearly 0V. As a result, the current flowing out from ZC pin can be calculated as I V BUS N a = -----------------------R ZC1 N P
ZC
[5]
When this current is higher than IZC_1, the amount of current exceeding this threshold is used to generate an offset to decrease the maximum limit on VCS. Since the ideal curve shown in Figure 6 is a nonlinear one, a digital block in CoolSET(R) - Q1 is implemented to get a better control of maximum output power. Additional advantage to use digital circuit is the production tolerance is smaller compared to analog solutions. The typical maximum limit on VCS versus the ZC current is shown in Figure 7.
1
0.9 Vcs-max(V)
0.8
0.7
0.6 300 500 700 900 1100 1300 1500 1700 1900 2100 Iz c(uA)
Figure 7
VCS-max versus IZC
3.5
Active Burst Mode Operation
At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption. Details
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Functional Description
Mode. This is helpful to decrease the output voltage undershoot. IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold VVCCoff, the startup cell is activated. The VCC capacitor is then charged up. Once the voltage exceeds the threshold VVCCon, the IC begins to operate with a new soft-start. In case of open control loop or output over load, the feedback voltage will be pulled up . After a blanking time of 24ms, the IC enters auto-restart mode. The blanking time here enables the converter to provide a high power in case the increase in VFB is due to a sudden load increase. During off-time of the power switch, the voltage at the zero-crossing pin is monitored for output over-voltage detection. If the voltage is higher than the preset threshold vZCOVP, the IC is latched off after the preset blanking time. If the junction temperature of IC exceeds 140 C, the IC enter into autorestart mode. If the voltage at the current sensing pin is higher than the preset threshold vCSSW during on-time of the power switch, the IC is latched off. This is short-winding protection. During latch-off protection mode, when the VCC voltage drops to 10.5V,the startup cell is activated and the VCC voltage is charged to 18V then the startup cell is shut down again and repeats the previous procedure. There is also an maximum on time limitation inside ICE2QR0665. Once the gate voltage is high longer than tOnMAx, it is turned off immediately.
VFB
VFBLB VFBBOn VFBBOff VFBEB
Entering Active Burst Mode
Leaving Active Burst Mode
Blanking Window (tBEB)
t
VCS
Current limit level during Active Burst Mode
1.0V VCSB
VVCC
t
VVCCoff
VO
Max. Ripple < 1%
t
t
Figure 8
Signals in Active Burst Mode
3.6
Protection Functions
The IC provides full protection functions. The following table summarizes these protection functions. Table 2 Protection features VCC Overvoltage VCC Undervoltage Overload/Open Loop Over temperature Output Overvoltage Short Winding Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Latched Off Mode Latched Off Mode
During operation, the VCC voltage is continuously monitored. In case of an under- or an over-voltage, the
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values min. max. 650 9.95 0.47 2.5 27 5.5 5.5 5.5 150 150 90 2
Unit
Remarks
Drain Source Voltage Pulse drain current, tp limited by Tjmax Avalanche energy, repetitive tAR limited by max. Tj=150C1) Avalanche current, repetitive tAR limited by max. Tj=150C VCC Supply Voltage FB Voltage ZC Voltage CS Voltage Maximum current out from ZC pin Junction Temperature Storage Temperature Thermal Resistance Junction -Ambient ESD Capability (incl. Drain Pin)
1) 2)
VDS ID_Puls1 EAR1 IAR1 VVCC VFB VZC VCS IZCMAX Tj TS RthJA VESD
-0.3 -0.3 -0.3 -0.3 3 -40 -55 -
V A mJ A V V V V mA C C K/W kV
Tj=110C Tj=125C
Controller & CoolMOS(R)
Human body model2)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol Limit Values min. max. VVCCOVP V Unit Remarks
Parameter
VCC Supply Voltage
VVCC
VVCCoff
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Electrical Characteristics
Junction Temperature of Controller TjCon Junction Temperature of CoolMOS(R) TjCoolMOS -25 -25 130 150 C C limited by over temperature protection
4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 125 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Symbol min. Limit Values typ. 300 5.0 1 0.2 1.5 300 max. 550 2 50 2.3 A mA mA mA mA A mA A VVCC =VVCCon -0.2V VVCC = 0V VVCC = 1V VVCC =VVCCon -0.2V VVCC =VVCCon -0.2V VDrain = 610V at Tj=100C output low IFB = 0A Unit Test Condition
Parameter
Start Up Current VCC Charge Current
IVCCstart IVCCcharge1 IVCCcharge2 IVCCcharge3
0.8 -
Maximum Input Current of Startup Cell and CoolMOS(R) Leakage Current of Startup Cell and CoolMOS(R) Supply Current in normal operation Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Latch-off Mode Supply Current in Burst Mode with inactive Gate VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis 4.3.2 Parameter
IDrainIn IDrainLeak IVCCNM IVCCAR
IVCClatch IVCCburst
-
300 500
950
A A VFB = 2.5V, exclude the current flowing out from FB pin
VVCCon VVCCoff VVCChys
17.0 9.8 -
18.0 10.5 7.5
19.0 11.2 -
V V V
Internal Voltage Reference Symbol min. Limit Values typ. 5.00 max. 5.20 V Measured at pin FB IFB=0 Unit Test Condition
Internal Reference Voltage
VREF
4.80
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Electrical Characteristics
4.3.3 Parameter PWM Section Symbol min. Feedback Pull-Up Resistor PWM-OP Gain Offset for Voltage Ramp Maximum on time in normal operation 4.3.4 Parameter Current Sense Symbol min. Peak current limitation in normal operation Leading Edge Blanking time Peak Current Limitation in Active Burst Mode 4.3.5 Soft Start VCSth tLEB VCSB 0.97 200 0.29 Limit Values typ. 1.03 330 0.34 max. 1.09 460 0.39 V ns V Unit Test Condition RFB GPWM VPWM tOnMax 14 3.18 0.6 22 Limit Values typ. 23 3.3 0.7 30 max. 33 41 k V s Unit Test Condition
Parameter
Symbol min.
Limit Values typ. 12 3 1.76 0.56 max. -
Unit
Test Condition
Soft-Start time soft-start time step Internal regulation voltage at first step Internal regulation voltage step at soft start
1)
tSS tSS_S1) VSS11) VSS_S1)
8.5 -
ms ms V V
The parameter is not subjected to production test - verified by design/characterization Foldback Point Correction Symbol min. Limit Values typ. 0.5 1.7 0.66 max. 0.621 2.2 mA mA V Izc=2.2mA, VFB=3.8V Unit Test Condition
4.3.6 Parameter
ZC current first step threshold ZC current last step threshold CS threshold minimum
IZC_FS IZC_LS VCSMF
0.350 1.3 -
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Electrical Characteristics
4.3.7 Parameter Digital Zero Crossing Symbol min. Zero crossing threshold voltage Ringing suppression threshold VZCCT VZCRS 50 1.62 Limit Values typ. 100 0.7 2.5 25 3.9 3.2 2.5 2.9 2.3 1.3 0.8 48 30 42 57.5 max. 170 4.5 mV V s s V V V V V mA mA ms s VZC > VZCRS VZC < VZCRS Unit Test Condition
Minimum ringing suppression time tZCRS1 Maximum ringing suppression time Threshold to set Up/Down Counter to one Threshold for downward counting at low line Threshold for upward counting at low line Threshold for downward counting at hig line Threshold for upward counting at highline ZC current for IC switch threshold to high line ZC current for IC switch threshold to low line Counter time1) Maximum restart time in normal operation
1)
tZCRS2 VFBR1 VFBZHL VFBZLL VFBZHH VFBZLH IZCSH IZCSL tCOUNT tOffMax
The parameter is not subjected to production test - verified by design/characterization Active Burst Mode Symbol min. Limit Values typ. 1.25 7 24 4.5 3.6 3.0 ms V V V max. V Unit Test Condition
4.3.8 Parameter
Feedback voltage for entering Active Burst Mode Minimum Up/down value for entering Active Burst Mode Blanking time for entering Active Burst Mode Feedback voltage for leaving Active Burst Mode Feedback voltage for burst-on Feedback voltage for burst-off
VFBEB NZC_ABM tBEB VFBLB VFBBOn VFBBOff
-
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Electrical Characteristics
Fixed Switching Frequency in Active Burst Mode Max. Duty Cycle in Active Burst Mode 4.3.9 Parameter Protection Symbol min. VCC overvoltage threshold Over Load or Open Loop Detection threshold for OLP protection at FB pin Over Load or Open Loop Protection Blanking Time Output Overvoltage detection threshold at the ZC pin Blanking time for Output Overvoltage protection Threshold for short winding protection Blanking time for short-windding protection Over temperature protection1) Note: 4.3.10 VVCCOVP VFBOLP 24.0 Limit Values typ. 25.0 4.5 max. 26.0 V V Unit Test Condition fsB DmaxB 39 52 0.5 65 kHz
tOLP_B VZCOVP tZCOVP VCSSW tCSSW TjCon
20 3.55
30 3.7 100
44 3.84
ms V s
1.63 130
1.68 190 140
1.78 150
V ns C
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP CoolMOS(R) Section
Parameter
Symbol min.
Limit Values typ. 0.65 1.37 261) 302) 302) max. 0.75 1.58 -
Unit
Test Condition
Drain Source Breakdown Voltage Drain Source On-Resistance
V(BR)DSS RDSon1
650 -
V pF ns ns
Tj = 110C Tj = 25C Tj=125C1) at ID = 2.5A VDS = 0V to 480V
Effective output capacitance, energy related Rise Time Fall Time
1) 2)
Co(er) trise tfall
-
The parameter is not subjected to production test - verified by design/characterization Measured in a Typical Flyback Converter Application
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Typical CoolMOS(R) Performance Characteristic
5
Typical CoolMOS(R) Performance Characteristic
Figure 9
Safe Operating Area(SOA) curve for ICE2QR0665
Figure 10
Power dissipation; Ptot=f(Ta)
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Typical CoolMOS(R) Performance Characteristic
Figure 11
Drain-source breakdown voltage; VBR(DSS)=f(Tj)
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Input power curve
6
Input power curve
Two input power curves gives typical input power versus ambient temperature are showed below; Vin=85~265Vac(Figure 12) and Vin=230Vac(Figure 13). The curves are derived based on a typical discontinuous mode flyback model which considers 115V maximum secondary to primary reflected voltage(high priority). The calculation is based on no copper area as heatsink for the device. The input power already includes power loss at input comman mode choke and bridge rectifier and the CoolMOS(R). The device saturation current(ID_plus@Tj=125 C) is also considered. To estimate the out power of the device, it is simply multiplying the input power at a particulary ambient temperature with the estimated efficiency for the application. For example, a wide range input voltage(Figure 12), operating temperature is 50 C, estimated efficiency is 85%,the output power is 42.5W(50W*0.85).
70
Input Power(85Vac~265Vac)[W]
60
50
40
30
20
10
0 0 25 35 45 55 65 75 85
0
95
105
115
125
Ambient Temperature[ C ]
Figure 12
Input Power curve Vin=85~265Vac;Pin=f(Ta)
120
100
Input Power(230Vac)[W]
80
60
40
20
0 0 25 35 45 55 65 75 85
0
95
105
115
125
Am b ien t T em p eratu re[ C ]
Figure 13
Input Power curve Vin=230Vac;Pin=f(Ta)
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Outline Dimension
7
Outline Dimension
PG-DIP-8-6 / PG-DIP-8-9 (Leadfree Plastic Dual In-Line Outline)
Figure 14
PG-DIP-8-6, PG-DIP-8-9 (Pb-free lead plating Plastic Dual-in-Line Outline)
Dimensions in mm
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Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
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